A phase frequency detector (PFD) is a device which compares the phase of two input signals. The PFD includes two inputs which correspond to two different input signals, usually one from a voltage-controlled oscillator (VCO) and another from other external sources. The PFD has two outputs which instruct subsequent circuitry how to adjust the frequency to lock onto the phase of the reference signal. To form a phase-locked loop (PLL), a PFD phase error output is transmitted to a loop filter which integrates the signal to smooth it. The smoothed signal is transmitted to a VCO which generates an output signal with a frequency that is proportional to the input voltage. The VCO output is also transmitted back to the PFD to lock into phase with the reference signal.
A pump converts the PFD digital phase error to an analog charge. The PFD and pump of a traditional tracking loop (i.e., signal path) is disabled when the PLL operates in a realignment mode. As a result, the PLL is not capable of recovering the target frequency in realignment mode when the PLL suffers from temperature variation. In order to recover the target frequency, the traditional tracking loop is enabled. In the tracking loop, the PFD and pump convert the phase difference of a reference and feedback clock to a voltage for finely adjusting frequency of the oscillator. In the realignment loop, the reference clock directly aligns the phase of the oscillator. When two loops are enabled together, two instructions are injected into a ring oscillator of the PLL at the same time to create a loop conflict, which refers to a situation when there is a traditional tracking loop and a realignment loop in the circuit. The worst case scenario conflict occurs at the realignment strength of 1:1, which creates spurs at high frequency. As discussed in further detail below, “realignment strength”, also known as loop weight, reflects the relative strength between the traditional tracking loop and the realignment loop. A “spur” is a peak in the log-log plot of the power spectral density figure. In order to reduce conflict and improve integrated jitter, the realignment strength can be adjusted.
In conventional approaches, the conflict of a traditional loop and a realignment loop is controlled by adjusting the strength of realignment. A weak realignment reduces the conflict between two loops, however, the corresponding rise in integrated jitter poses problems. A strong realignment suppresses the in-band noise of PLL, but the out-band spur is generated by strong conflict to degrade integrated jitter.
The realignment improves integrated jitter of the PLL by aligning the phase of the ring oscillator with the reference clock. When the PLL operates in the realignment mode, the PFD and pump of a traditional tracking loop is disabled to avoid a loop conflict. In this scenario, the PLL frequency can't be recovered in realignment mode when the PLL suffers temperature variation when the tracking loop is disabled. As a result, the traditional tracking loop must be enabled to trace a target frequency when the PLL suffers temperature variation.